In general, programmable logic devices (PLDs) permit a user to configure the PLD device to accommodate a wide spectrum of applications. One type of PLDs has a programmable macro cell. The programmable macro cell provides the capability of defining the architecture of each output individually. Each of the potential outputs may be specified to be "registered" or "combinatorial". In addition, the polarity of each output may also be individually selected allowing complete flexibility of the output configuration. In addition, further configurability is provided through "array" configurable "output enable" for each potential output. This feature allows the outputs to be reconfigured as inputs on an individual basis, or alternatively, used as a combinational I/O controlled by the programmable array. An example of such a PLD device is manufactured by Cypress Semiconductor Corporation, the Assignee of the present invention.
FIG. 1 illustrates a user configurable macro cell configured in accordance with the prior art. For the circuit illustrated in FIG. 1, the user selects the configuration of the macro cell to operate as either a D-type flip-flop or a T-type flip-flop. In addition, the user selects the polarity of the output data (e.g. whether the output of the circuit is selected from the register true (Q) or bar (Q)). Typically, the user selects the configuration by programming user configurable bits. In response to the user configurable bits, a D-type, a T-type, a polarity, Dtype, a Ttype and polarity select signals are generated. A macrocell 100 receives the D-type, T-type, polarity, Dtype, Ttype and polarity select signals.
The macro cell circuit 100 contains an exclusive OR gate (XOR) 102, a register 120, and a plurality of transmission gates 105, 110, 152 and 154. The XOR gate 102 implements the toggle function for the T-type flip-flop. As is shown in FIG. 1, transmission gates 105, 110, 115, 125, 140, 148, 154 and 152 contain a p channel metal oxide semiconductor (MOS) transistor and an n channel MOS transistor. The register 120, used to implement the D-type and the T-type flip-flops, contains a master latch, a slave latch and a transmission gate 140 used to couple the master latch and the slave latch. The master latch includes inverters 130 and 135, as well as transmission gate 125. The slave latch includes inverters 145 and 146, as well as transmission gate 148.
The "Data In" is input to the XOR 102 and a transmission gate 105. If a D-type flip-flop is specified by the static control signals, then the transmission gate 105 conducts the "data in" signal to a transmission gate 115. If the static control signals specify a T-type flip-flop, then the output of the XOR gate 102 is coupled to the transmission gate 115 via the transmission gate 110.
During a clock transition from a high state to low logic state, the data input to transmission gate 115 is passed to the master latch. Also, during the high state to low logic state transition, the transmission gates 125 and 140 are closed, and the transmission gate 148 is open to latch or retain the state previously latched in the slave latch. When the clock cycle transitions to a high logic level, the transmission gate 140 and the transmission gate 125 are opened to latch the data in the master latch, and to pass the data into the slave latch, inverters 145 and 146. In addition, in the high clock cycle, the transmission gate 148 is closed. The polarity and polarity static signals select either the true or bar outputs of the register 120 to generate the "data out".
Although the macro cell circuit 100 provides selectable D-type or T-type configurations, the T-type configuration requires a longer set-up time than the D-type configuration due to the XOR gate 102. In addition, the data path for the D-type configuration includes transmission gate 105, and the data path for the T-type configuration includes transmission gate 110. Furthermore, whether the T-type or D-type configurations are selected, the data is further delayed by the transmission gates 152 and 154 utilized to select the polarity.